1. Field of the Invention
The present invention relates to a synchronous output buffer, a synchronous memory device and a method of testing access time, more particularly to an output buffer of a double data rate synchronous dynamic random access memory (DDR-SDRAM), a synchronous memory device and a method of testing access time.
2. Description of the Related Art
As the multimedia industry continues to develop and as system operation speeds continue to increase, memory devices having higher speed, higher functionality and lower power consumption are needed. For this reason, several popular memory technologies, including Rambus DRAM, DDR SDRAM, PC133 standardized SDRAM, etc., are in competition for market share.
The DDR is currently the technical standard of the next generation DRAM having high operation speeds, and can be manufactured using conventional production equipment. In a DDR, the transfer rate of data is doubled so as to enhance the overall operation speed. The DDR is one of the high-speed memory device technologies that have been adopted by Joint Electronic Device Engineering Council (JEDEC), an international standardization organization, in 1997.
As the operation speed of the memory device becomes higher, improved accuracy is require in various parameters and in specification of the operation speed. One of the most important timing parameters of associated with the operation speed is address access time tAA. The address access time tAA represents the elapsed time from the clock edge to data output.
The address access time tAA parameter is represented in the following equation,tAA=tCK×(CL−1)+tAC,
wherein tCK represents the time duration of the clock cycle, CL(CAS Latency) is a number obtained by dividing the time from the input of a read output signal to the output of effective data by the time of the clock cycle, and tAC represents access time from the front edge of the clock to the output of effective data. In this manner, precise measurement of the tAA and tAC parameters is required so as to test the performance of a memory chip device.
An AC parameter test is performed so as to test whether various AC parameters are satisfactory in accordance with a design. When an operator of the AC parameter test is not particularly skilled, incorrect test results may be induced due to the limitations of the measuring device. As a result, faulty designs or products may pass through the test as fully functional.